TSMC · one lens
Hamilton Helmer on TSMC
Two of Helmer's rarest Powers, scale and process, compounding on the same balance sheet at once.
Scale Economies and Process Power are different Barriers with the same shape in Helmer’s framework: both punish a challenger who tries to catch up by spending, because the thing that needs matching — accumulated volume in one case, accumulated organizational learning in the other — can’t be bought in a single check (7 Powers). TSMC’s record shows both operating on the same business at once.
Scale first. TSMC’s 2026 capex guidance, raised to $60B–$64B in its most recent quarter (texxr.com/1173080), is the fixed-cost commitment Helmer’s chapter describes: spread across the industry’s largest wafer volume, it produces a cost-per-chip a smaller foundry can’t match without first matching the volume — and it can’t profitably win that volume away, because the leader can defend share at a price the challenger can’t survive. Q2 2026 revenue, up 36% year over year to roughly $39.45B (texxr.com/1173046), is that gap compounding rather than closing.
Process Power is the second, and the one Helmer calls rarest because it requires decades, not capital. Chips at 7 nanometers or smaller made up 77% of TSMC’s wafer revenue that same quarter (texxr.com/1173046) — a lead built on accumulated fab tuning that a January 2026 Stratechery piece, arguing the industry needs to “build up Samsung or Intel as rivals,” still treated as unclosed even with both rivals trying (texxr.com/1162139). A year earlier, Reuters reported TSMC’s own top customers had pitched it on helping fund a joint venture to run Intel’s foundry (texxr.com/883401) — a rival’s rescue routed through the leader’s balance sheet, about as clear a sign as the record offers that the process gap isn’t one capital alone can close.
The two Powers reinforce each other: scale funds the next node, the next node retains the scale. The one line worth tracking is the one already moving — competitor-framed edges in TEXXR’s graph, effectively nonexistent in 2024, now 9.2% of TSMC’s most recent batch.
The seven Powers, one by one
| Power | Status | Why |
|---|---|---|
| Scale Economies | held | 2026 capex guided to $60B-$64B spread over the industry's largest wafer volume; Q2 2026 revenue up 36% YoY to ~$39.45B — the cost gap compounding, not closing |
| Network Economies | absent | not argued in the record |
| Counter Positioning | absent | not argued in the record |
| Switching Costs | absent | not argued in the record |
| Branding | absent | not argued in the record |
| Cornered Resource | absent | not argued in the record |
| Process Power | held | chips at 7nm-or-smaller are 77% of wafer revenue; Samsung and Intel still haven't closed the gap per a Jan 2026 Stratechery piece, and TSMC's own top customers pitched funding a rescue of Intel's foundry through TSMC's balance sheet |
An editorial application of Hamilton Helmer's published framework — not their actual view, affiliation, or advice.
Where this lens comes from
Hamilton Helmer's framework is set out at the lens page, drawn from 7 Powers. This page applies it to TSMC and nothing else — the company's full record is in the dossier.